BossAgentsChip Design 40-Second Closed Loop: LLM Generation Meets Instant Verification
Two old paths, one deadlock
Using AI to write Verilog now basically comes down to two paths:
1. Pure LLM generation: the code looks right but doesn't compile—the registers produced by hallucination are not recognized by synthesis tools;
2. Traditional EDA (Vivado/DC and the like): closed-source, expensive, no AI assistance—RTL is still written by humans.
ChipWise takes a third path: the LLM handles generation and understanding, while the open-source EDA toolchain handles verification—generation means verification; anything that fails is automatically repaired until compilation, Lint, and simulation all pass.
8-step closed loop, ~40 seconds end-to-end
| 步骤 | 能力 | 执行引擎 | 实测延迟 |
|---|---|---|---|
| ① 工具链检测 | EDA 健康检查 | 本地 | 超时保护 |
| ② 规格识别 | identify | Ollama 端侧 | ~2s |
| ③ RTL Generate | create | 云端强模型 | ~20s |
| ④ 编译+Lint | iverilog + Verible | 本地 | ~8s |
| ⑤ 规则检查 | 47 条（含 12 条 IEEE） | 本地 | ~1s |
| ⑥ 关系分析 | 模块依赖+信号链 | 本地关系引擎 | ~1s |
| ⑦ 仿真验证 | testbench 执行 | iverilog+VVP | ~8s |
| ⑧ 时间线汇总 | 全流程追溯 | 本地 | ~5s |
From a natural-language specification to RTL that passes compilation, Lint, and simulation—in 40 seconds. The toolchain (Icarus Verilog / Yosys / Verible / riscv-gcc) runs entirely locally.
Measured hard data (RV32I five-stage pipeline POC)
- iverilog compilation: 0 errors style="padding-left:20px;margin:12px 0;">
- verible lint: 0 errors style="padding-left:20px;margin:12px 0;">
- yosys synthesis succeeded: 4,069 cells / 992 flip-flops
Limitations, honestly.
Step ③ RTL generation uses a strong cloud model—the on-device 7B model proved insufficient in testing, and we won't force it. In the entire closed loop, the on-device side handles recognition, rule checking, relationship analysis, and simulation verification (spanning 7 steps), while strong generation is left to wherever it can be properly delivered. This is not a "fully on-device" promotional video; it is a workable engineering trade-off.
BossAgents (Left and Right Hands): ChipWise Engine, with all six capabilities (recognition/creation/repair/comparison/optimization/generation) fully implemented, a work validated at the HICOOL semifinals.
All data in this article can be traced in the BossAgents technical documentation library · Left and Right Hands · Boss's private AI agent
